There will be a combined poster session at ISCA 2022 for authors of papers accepted at ISCA 2020, 2021, and 2022 to present their papers. This gives the opportunity for authors who presented online in the prior years to have the opportunity to present in person. See the list of poster titles below.

At a Glance

  • The ISCA 2020, 2021, and 2022 poster session will be held Monday June 20, 2022 at 6:30pm EDT.
  • Typical poster size is 48 inches x 36 inches.
  • Presenters must bring their posters with them.
  • We sent a form to be filled by authors and we received 51 responses. If you still want to present your poster, please email the General Chairs ( with the subject line "poster presentation in ISCA" and an email body containing the paper title and ISCA year.
  • Poster Presentation Request Deadline: May 20, 2022

Jump to Posters of ISCA 2020 | ISCA 2021 | ISCA 2022

ISCA 2020

Paper Title
Lelantus: Fine-Granularity CopyOn-Write Operations for Secure Non-Volatile Memories
Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial Hardware Prefetching
Hardware-based domain virtualization for intra-process isolation of persistent memory objects
uGEMM: Unary Computing Architecture for GEMM Applications
SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation
Packet Chasing: Spying on Network Packets over a Cache Side-Channel
DSAGEN: Synthesizing Programmable Accelerators
Perforated Page: Supporting Fragmented Memory Allocation for Large Pages
Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution
CryoCore: A Fast and Dense Processor Architecture for Cryogenic Computing
Hardware-Software Co-Design for Brain-Computer Interfaces
TransForm: Formally Specifying Transistency Models and Synthesizing Enhanced Litmus Tests
Enhancing and Exploiting Contiguity for Fast Memory Virtualization
DSAGEN: Synthesizing Programmable Accelerators
Nested Enclave: Supporting Fine-grained Hierarchical Isolation with SGX
HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols
T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives

Jump to Posters of ISCA 2020 | ISCA 2021 | ISCA 2022

ISCA 2021

Paper Title
PMNet: in-network data persistence
Dve: Improving DRAM Reliability andPerformance On-Demand via Coherent Replication
Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications
Rebooting Virtual Memory with Midgard
Superconducting Computing with Alternating Logic Elements
Quantifying Server Memory Frequency Margin and Using it to Improve Performance in HPC Systems
Opening Pandora’s Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data
PolyGraph: Exposing the Value of Flexibility for Graph Processing Accelerators.
CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing
Exploiting Page Table Locality for Agile TLB Prefetching
Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching
Efficient Multi-GPU Shared Memory via Automatic Optimization of Fine-Grained Transfers
Don't Forget the I/O When Allocating Your LLC
A Cost-Effective Entangling Prefetcher for Instructions
Taming the Zoo: A Unified Graph Compiler Framework for Novel Architectures
NN-Baton: DNN Workload Orchestration and Chiplet Granularity Exploration for Multichip Accelerators
TimeCache: using time to eliminate cache side channels when sharing software
Dual-side sparse tensor core
Leaky buddies: Cross-component covert channels on integrated cpu-gpu systems
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators
CODIC: A low-cost substrate for enabling custom in-DRAM functionalities and optimizations
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators
IntroSpectre: A Pre-Silicon Framework for Discovery and Analysis of Transient Execution Vulnerabilities
Maya: Using Formal Control to Obfuscate Power Side Channels
Cost-Efficient Overclocking in Immersion-Cooled Datacenters
SpZip: Architectural Support for Effective Data Compression In Irregular Applications
Unlimited Vector Extension with Data Streaming Support
Communication Algorithm-Architecture Co-Design for Distributed Deep Learning
Jump to Posters of ISCA 2020 | ISCA 2021 | ISCA 2022

ISCA 2022

Paper Title
uBrain: A Unary Brain Computer Interface
Thermometer: Profile-Guided BTB Replacement for Data Center Applications
Gearbox: A Case for Supporting Accumulation Dispatching and Hybrid Partitioning in PIM-based Accelerators
XQsim: Modeling Cross-Technology Control Processors for 10+K Qubit Quantum Computers
Mixed-Proxy Extensions for the NVIDIA PTX Memory Consistency Model
Axiomatic Hardware-Software Contracts for Security
MOESI-prime: Preventing Coherence-Induced Hammering in Commodity Workloads
GCoM: A Detailed GPU Core Model for Accurate Analytical Modeling of Modern GPUs
NDMiner: Accelerating Graph Pattern Mining Using Near Data Processing
täkō: A Polymorphic Cache Hierarchy for General-Purpose Optimization of Data Movement
A Scalable Architecture for Reprioritizing Ordered Parallelism
SNS’s not a Synthesizer: A Deep-Learning-Based Synthesis Predictor
Graphite: Optimizing Graph Neural Networks on CPUs Through Cooperative Software-Hardware Techniques
EyeCoD: Eye Tracking System Acceleration via FlatCam-Based Algorithm and Accelerator Co-Design
Cascading Structured Pruning: Enabling High Data Reuse for Sparse DNN Accelerators
Themis: A Network Bandwidth-Aware Collective Scheduling Policy for Distributed Training of DL Models
Tiny but Mighty: Designing and Realizing Scalable Latency Tolerance for Manycore SoCs