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ISCA 2021
June 14–19, 2021
Workshops & Tutorials
Morning
(
EDT
)
Afternoon
(
EDT
)
Thu
rsday,
June 17
CARRV (RISC-V)
workshop
9 AM – 3 PM
(
EDT
/New York)
5th RISC-V Computer Architecture Research Workshop
CLEAR
workshop
9 AM – 3 PM
(
EDT
/New York)
Computing Landscapes with Environmental Accountability and Responsibility Workshop
DRAMSec
workshop
9 AM – 3 PM
(
EDT
/New York)
1st Workshop on DRAM Security
WCAE
workshop
9 AM – 3 PM
(
EDT
/New York)
Workshop on Computer Architecture and Education
AIBench
tutorial
9 AM – 3 PM
(
EDT
/New York)
Distilling Real-World Applications into AI Scenario, Training, and Inference Benchmarks Across Datacenter, HPC, IoT and Edge
AccelTraining
tutorial
9 AM – 12 PM
(
EDT
/New York)
Hardware Accelerators for Training Deep Neural Networks
Voltage
tutorial
12 PM – 3 PM
(
EDT
/New York)
Methods for Characterization and Analysis of Voltage Margins in Modern CPUs, GPUs, and FPGAs
Morning
(
EDT
)
Afternoon
(
EDT
)
Fri
day,
June 18
SPSL
workshop
9 AM – 3 PM
(
EDT
/New York)
Secure and Private Systems for Machine Learning
I2Q
workshop
9 AM – 3 PM
(
EDT
/New York)
I Too Can Quantum!
FireSim / Chipyard
tutorial
9 AM – 3 PM
(
EDT
/New York)
End-to-End Architecture Research with RISC-V SoC Generators, Agile Test Chips, and FPGA-Accelerated Simulation on Amazon EC2 F1
uArch
workshop
9 AM – 3 PM
(
EDT
/New York)
3rd Annual Undergraduate Architecture Mentoring Workshop
DistDeep
tutorial
9 AM – 12 PM
(
EDT
/New York)
High Performance Distributed Deep Learning: A Beginner's Guide
DeepBench
tutorial
12 PM – 3 PM
(
EDT
/New York)
A Deep Dive into Deep Learning Benchmarking and Analysis
ILLIXR
tutorial
9 AM – 12 PM
(
EDT
/New York)
Illinois Extended Reality Testbed
MechaFlow
tutorial
12 PM – 3 PM
(
EDT
/New York)
Democratizing AI Hardware Landscape Evaluation and Exploration
Morning
(
EDT
)
Afternoon
(
EDT
)
Sat
urday,
June 19
AIDArc
workshop
9 AM – 3 PM
(
EDT
/New York)
4th International Workshop on AI-Assisted Design for Architecture
MLArchSys
workshop
9 AM – 3 PM
(
EDT
/New York)
Machine Learning for Computer Architecture and Systems
QRE
workshop
9 AM – 3 PM
(
EDT
/New York)
3rd Workshop on Quantum Resource Estimation
Xilinx HPC
tutorial
9 AM – 3 PM
(
EDT
/New York)
Developing HPC Accelerators Using Xilinx FPGAs
SCALE-Sim
tutorial
9 AM – 12 PM
(
EDT
/New York)
Systolic CNN Accelerator Simulator
Sparse Tensor
tutorial
12 PM – 3 PM
(
EDT
/New York)
Sparse Tensor Accelerators: Abstraction and Modeling