The fields of computer and information science and engineering (CISE) are central to nearly all of society's needs, opportunities, and challenges. The US National Science Foundation (NSF) was created 70 years ago with a broad mission to promote the progress of science and to catalyze societal and economic benefits. NSF, largely through its CISE directorate which has an annual budget of more than $1B, accounts for over 85% of federally-funded, academic, fundamental computer science research in the US. My talk will give an overview of NSF/CISE research, education, and research infrastructure programs, and relate them to the technical and societal trends and topics that will impact their future trajectory. I will particularly highlight opportunity areas most in need of the engagement and insights from ISCA researchers going forward.
Margaret Martonosi is the US National Science Foundation's (NSF) Assistant Director for Computer and information Science and Engineering (CISE). With an annual budget of more than $1B, the CISE directorate at NSF has the mission to uphold the Nation's leadership in scientific discovery and engineering innovation through its support of fundamental research and education in computer and information science and engineering as well as transformative advances in research cyberinfrastructure. While at NSF, Dr. Martonosi is on leave from Princeton University, where she is the Hugh Trumbull Adams '35 Professor of Computer Science.
Dr. Martonosi's research interests are in computer architecture and hardware-software interface issues in both classical and quantum computing systems. Her work has included the widely-used Wattch power modeling tool and the Princeton ZebraNet mobile sensor network project for the design and real-world deployment of zebra tracking collars in Kenya. Dr. Martonosi is a member of the American Academy of Arts and Sciences, and a Fellow of the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE). Her papers have received numerous long-term impact awards from the computer architecture and mobile computing communities. In addition, she has earned the 2019 SIGARCH Alan D. Berenbaum Distinguished Service Award, the 2018 IEEE Computer Society Technical Achievement Award, and the 2010 Princeton University Graduate Mentoring Award, among other honors.
This panel will discuss where the security research in computer architecture is heading and how the field can have more impact going forward. For example, the panel will discuss questions such as what are the major open problems and research directions in processor security, how can computer architects improve the security landscape, what is the role of hardware in improving system security, how can academic research communities effectively work together with industry researchers, etc.
The panel will include brief position statements by the participants plus a Q&A format where each panelist will respond to questions from the audience. The panelists will also have some questions prepared.
The last decade has seen a remarkable shift towards research on hardware accelerators — particularly domain-specific accelerators — both in academia and industry. The promise of accelerators is to shed the dead weight of traditional execution models, and enable data orchestration, parallelism, and even arithmetic that is precisely tailored to application needs. Academic papers report multiple orders of magnitude improvement, and industry has seen proliferation of hardware accelerators in software companies (TPU, Brainwave) and in numerous hardware startups.
Yet, due to a number of fundamental challenges, the future of this new wave of computing machines remains largely uncertain. For one, accelerators require unique hardware/software interfaces, meaning that robust software stacks for accelerators are time consuming and difficult to create. This can make accelerator systems difficult to program effectively in a way that can keep up with algorithm evolution. Accelerators are often narrow, and aren't useful for broad domains, making them somewhat niche machines. In order to use them, algorithms are often expressed inefficiently in limited interfaces. More broadly, in the CS community outside of architecture, many simply give up on using today's accelerators (e.g., TPUs, GPU tensor cores) because of the complexities and uncertain benefits.
In this mini-panel, our panelists will discuss their views on these challenges and implications on the future of accelerator research. The panelists will also invite questions from the live audience.
This panel will talk about AI, ML, and how the architecture community interacts with those fields. We'll consider a number of questions that relate to work going on in industry and academia, how they differ, and how much algorithms and architecture will change what we need to be doing. We'll consider questions such as:
The pace of innovation in computing systems, and thus the electronic industry, is being impacted by slowing trends in traditional device scaling, and by skyrocketing costs of design and manufacturing. The high level of engineering specialization and the high-cost barriers to enter the electronics market has shrunk the number of startups and companies that can participate in the design of novel computing systems. In this talk, I will argue that the key to reignite innovation in computing systems design is to enable participation by a broader engineering community. To attain this goal, it is necessary to transform current design and creative processes with a meaningful level of automation in the front-end stages of the design process. In this context, domain-specific languages, or DSLs, enable broader participation in the building of efficient and effective applications. Coupled with a turnkey, end-to-end eco-system of flexible hardware accelerators, which can serve as highly efficient compiler targets for applications, it becomes possible for small teams to realize big ideas. The talk will share perspectives from a large research center focused on these initiatives. The next step to catalyze this transformation will be to automate the design of new hardware accelerators, to quickly address emerging applications with domain-efficient computation.
Valeria Bertacco is Thurnau Professor of Electrical Engineering and Computer Science at the University of Michigan, and Adjunct Professor of Computer Engineering at the Addis Ababa Institute of Technology. Her research interests are in the area of computer design, with emphasis on specialized architecture solutions and design viability, in particular reliability, validation, and hardware-security assurance. She joined the University of Michigan in 2003, after working with the Advanced Technology Group of Synopsys, which she joined via the acquisition of Systems Science Inc. When the world is not engulfed in a pandemic, Valeria enjoys traveling the world to find new and exciting adventures and collaborations.
Valeria is the Director of the Applications Driving Architectures (ADA) Research Center, whose goal is to reignite computing systems design and innovation for the 2030-2040s decades, through specialized heterogeneity, domain-specific language abstractions and new silicon devices that show benefit to applications. The Center engages 21 faculty members and 130 students from 10 academic institutions in the United States. During her career, she has served as the Program Chair of the Design Automation Conference (DAC), Track Chair of the Design Automation and Test in Europe (DATE) Conference, and asAssociate Editor of the IEEE Transactions on Computer-Aided Design. Valeria is the recipient of the IEEE CEDA Early Career Award, NSF CAREER award, the Air Force Office of Scientific Research's Young Investigator award and the IBM Faculty Award. From the University of Michigan, she received the Vulcans Education Excellence Award, the Herbert Kopf Service Excellence Award, the Sarah Goddard Power Award for contribution to the betterment of women, the Rackham Faculty Recognition Award and the Harold Johnson Diversity Service Award. Valeria is an ACM Distinguished Scientist and an IEEE Fellow.
People increasingly rely on data center services to carry out their day-to-day tasks ranging from business transactions and democratizing information, to education, entertainment, and life experiences. The sheer amount of data shifted through and computed through the network, processors and storage daily is staggering. This panel aims to have a thought-provoking discussion on the latest trends and novel research directions in data center hardware and system architectures. The panelists plan to touch on several of the following topics:
In this mini-panel, each panelist will present a short overview on the challenges and research directions for future data center architecture and services, and then we'll open up the floor to questions from the audience.
The current state of quantum computing is often compared to classical computing in the 1950s, where the fundamental building blocks existed but the full-fledged system stack did not. Another camp argues that quantum technology is much closer to classical hardware of 1938. At this time it was unknown what technology was going to prevail or how they would be integrated to construct useful machines. In either case, we may regard the development of classical computers decades ago as a roadmap for the development of quantum computers today. While quantum versions are inherently different and appear to pose greater challenges, knowledge gained from their classical counterparts can prove useful.
In the presence of challenges induced by quantum noise and ongoing attempts to demonstrate quantum supremacy/advantage, when it comes to taking classical concepts for abstraction, quantitative analysis (using performance, accuracy, metrics, etc.) or programmability, and assessing their adaptability to work for quantum systems, who can help more than computer architects and how? This question forms the focus of our panel.
Wearables will be as pervasive as phones. Yet, current wearables such as smartwatches and fitness trackers have fairly limited functionality. What lies ahead for wearables? In this talk, I will first take a look at the characteristics of wearable applications of the future, and discuss the implications on the architecture of next-generation wearable chips. I will then walk through recent research into wearable chip architectures and prototypes. Finally, the talk will round off with a glimpse into next-generation application scenarios for wearables.
Li-Shiuan Peh returned home to join National University of Singapore as Provost's Chair Professor in the Department of Computer Science, with a courtesy appointment in the Department of Electrical and Computer Engineering in September 2016. Previously, she was Professor of Electrical Engineering and Computer Science at MIT and was on the faculty of MIT since 2009. She was also the Associate Director for Outreach of the Singapore-MIT Alliance of Research & Technology (SMART) from 2015-2016. Prior to MIT, she was on the faculty of Electrical Engineering at Princeton University from 2002. She graduated with a Ph.D. in Computer Science from Stanford University in 2001, and a B.S. in Computer Science from the National University of Singapore in 1995. Her research focuses on networked computing, from chips to systems. Several of her papers received test-of-time, best paper and top picks awards at computer architecture, design automation and systems conferences. She is an IEEE Fellow.