Welcome Reception, Sponsored by Google

6:00 – 7:15 PM   
FCRC Plenary Speaker
Leslie G. Valiant, Harvard University    
2010 ACM Turing Lecture

Session 1: Novel Architectures (Exhibit Hall 3)
Chair: José F. Martínez, Cornell University

Automatic Abstraction and Fault Tolerance in Cortical Microarchitectures
Atif Hashmi (University of Wisconsin),Hugues Berry (INRIA Rhone-Alpes),Olivier Temam (INRIA Saclay),Mikko Lipasti (University of Wisconsin) (video)

FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template
Niket K. Choudhary,Salil V. Wadhavkar (North Carolina State University),Tanmay A. Shah (Intel Corporation),Hiran Mayukh,Jayneel Gandhi (University of Wisconsin - Madison),Brandon H. Dwiel,Sandeep Navada (North Carolina State University),Hashem H. Najaf-abadi (Intel Corporation),Eric Rotenberg (North Carolina State University) (video)

CRIB: Consolidated Rename, Issue, and Bypass
Erika Gunadi (Intel Corporation),Mikko H Lipasti (University of Wisconsin - Madison) (video)

Session 2: Parallel Architectures I (Exhibit Hall 3)
Chair: Babak Falsafi, Ecole Polytechnique Federale de Lausanne

FlexBulk: Intelligently Forming Atomic Blocks in Blocked-Execution Multiprocessors to Minimize Squashes
Rishi Agarwal, Josep Torrellas (UIUC) (video)

Virtualizing Performance Asymmetric Multi-core Systems
Youngjin Kwon,Changdae Kim,Seungryoul Maeng,Jaehyuk Huh (KAIST) (video)

Session 3A: Caches (Exhibit Hall 3)
Chair: Marcelo Cintra, University of Edinburgh

Vantage: Scalable and Efficient Fine-Grain Cache Partitioning
Daniel Sanchez,Christos Kozyrakis (Stanford University) (video)

Architecting On-Chip Interconnects for Stacked 3D STT-RAM Caches in CMPs
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, N. Vijaykrishnan, Chita R. Das (The Pennsylvania State University) (video)

Bypass and Insertion Algorithms for Exclusive Last-level Caches
Jayesh Gaur (Intel Corporation),Mainak Chaudhuri (Indian Institute of Technology),Sreenivas Subramoney (Intel Architecture Group) (video)

Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Data
Blas A Cuesta,Alberto Ros,María E Gómez,Antonio Robles,José F Duato (Universitat Politècnica de València) (video)

Session 3B: Parallel Architectures II (J)
Chair: Mark Hill, University of Wisconsin

TLSync: Support for Multiple Fast Barriers Using On-Chip Transmission Lines
Jungju Oh,Milos Prvulovic,Alenka Zajic (Georgia Institute of Technology) (video)

OUTRIDER: Efficient Memory Latency Tolerance with Decoupled Strands
Neal Clayton Crago,Sanjay Jeram Patel (University of Illinois at Urbana-Champaign) (video)

Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
Yunsup Lee,Rimas Avizienis,Alex Bishara,Richard Xia (University of California, Berkeley),Derek Lockhart,Christopher Batten (Cornell University),Krste Asanovic (University of California, Berkeley) (video)

Prefetch-Aware Shared Resource Management for Multi-Core Systems
Eiman Ebrahimi (The University of Texas at Austin),Chang Joo Lee (Intel Corporation),Onur Mutlu (Carnegie Mellon University),Yale Patt (The University of Texas at Austin) (video)

Session 4A: Dependable Architectures (Exhibit Hall 3)
Chair: Kim Hazelwood, University of Virginia

Rebound: Scalable Checkpointing for Coherent Shared Memory
Rishi Agarwal, Pranav Garg, Josep Torrellas (UIUC)

Demand-Driven Software Race Detection using Hardware Performance Counters
Joseph L. Greathouse (University of Michigan),Zhiqiang Ma,Matthew I. Frank,Ramesh Peri (Intel Corporation),Todd Austin (University of Michigan) (video)

Session 4B: Security (J)
Chair: Krste Asanovic, University of California, Berkeley

i-NVMM: A Secure Non-Volatile Main Memory System with Incremental Encryption
Siddhartha Chhabra,Yan Solihin (North Carolina State University) (video)

Crafting a Usable Microkernel Processor and I/O System with Strict and Provable Information Flow Security
Mohit Tiwari (University of California, Santa Barbara),Jason K Oberg (University of California, San Diego),Xun Li,Jonathan Valamehr (University of California, Santa Barbara),Timothy Levin (Naval Postgraduate School),Ben Hardekopf (University of California, Santa Barbara),Ryan Kastner (University of California, San Diego),Frederic T Chong,Timothy Sherwood (University of California, Santa Barbara) (video)

Session 5: Reliability (Exhibit Hall 3)
Chair: Ramon Canal, Universitat Politècnica de Catalunya

Sampling + DMR: Practical and Low-overhead Permanent Fault Detection
Shuou Nomura,Matthew D Sinclair,Chen-Han Ho,Venkatraman Govindaraju,Marc de Kruijf,Karthikeyan Sankaralingam (University of Wisconsin-Madison) (video)

Releasing Efficient Beta Cores Early to Market
Sangeetha Sudhakrishnan, Rigo Dicochea rigo, Jose Renau (University of California, Santa Cruz)  (video)

CPPC: Correctable Parity Protected Cache
Mehrtash Manoochehri, Murali Annavaram, Michel Dubois (University of Southern California) (video)

Session 6A: Multithreading (Exhibit Hall 3)
Chair: Per Stenström, Chalmers University of Technology

Energy-efficient Mechanisms for Managing Thread Context in Throughput Processors
Mark Gebhart (The University of Texas at Austin),Daniel R Johnson (University of Illinois at Urbana-Champaign),David Tarjan (NVIDIA),Stephen W Keckler (NVIDIA / The University of Texas at Austin),William J Dally (NVIDIA / Stanford University),Erik Lindholm (NVIDIA),Kevin Skadron (University of Virginia) (video)

SRAM-DRAM Hybrid Memory with Applications to Efficient Register Files in Fine-Grained Multi-Threading Architectures
Wing-kei Yu, Ruirui Huang, Sarah Xu, Sung-En Wang, Edwin Kan, G. Edward Suh (Cornell University) (video)

Session 6B: On-Chip Networks I (J)
Chair: Chita Das, Pennsylvania State University

An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing
Binzhang Fu,Yinhe Han,Jun Ma,Huawei Li,Xiaowei Li (Key Laboratory of Computer System and Architecture,Institute of Computing Technology, Chinese Academy of Sciences) (video)

A Case for Globally Shared-Medium On-Chip Interconnect
Aaron Carpenter, Jianyun Hu, Jie Xu, Michael Huang, Hui Wu (University of Rochester) (video)

Session 7A: Memory (Exhibit Hall 3)
Chair: Aamer Jaleel, Intel Research

The Impact of Memory Subsystem Resource Sharing on Datacenter Applications
Lingjia Tang,Jason Mars (University of Virginia),Neil Vachharajani (Pure Storage),Robert Hundt (Google),Mary Lou Soffa (University of Virginia) (video)

Adaptive Granularity Memory Systems: A Tradeoff between Storage Efficiency and Throughput
Doe Hyun Yoon, Min Kyu Jeong, Mattan Erez (The University of Texas at Austin) (video)

SpecTLB: A Mechanism for Speculative Address Translation
Thomas W. Barr, Alan L. Cox, Scott Rixner (Rice University) (video)

Session 7B: Power I   (J)
Chair: Pradip Bose, IBM Research

Power Management of On-line Data-Intensive Services
David Meisner (The University of Michigan),Christopher M Sadler,Luiz Andre Barroso,Wolf-Dietrich Weber (Google, Inc.),Thomas F. Wenisch (The University of Michigan) (video)

From Microns-to-Megawatts: Modeling the Data Center Scale Effects of Targeted Superlattice Thermal Management
Susmit Biswas (Lawrence Livermore National Laboratory),Mohit Tiwari,Timothy Sherwood,Luke Theogarajan,Frederic T Chong (University of California, Santa Barbara) (video)

Benefits and Limitations of Tapping into Stored Energy For Datacenters
Sriram Govindan, Anand Sivasubramaniam, Bhuvan Urgaonkar (The Pennsylvania State University) (video)

Session 8A: Architecture Modeling and Evaluation (Exhibit Hall 3)
Chair: Lieven Eeckhout, Ghent University

Rapid Identification of Architectural Bottlenecks via Precise Event Counting
John Demme, Simha Sethumadhavan (Columbia University)  (video)

Dark Silicon and the End of Multicore Scaling
Hadi Esmaeilzadeh (University of Washington),Emily Blem (University of Wisconsin-Madison),Renee St Amant (The University of Texas at Austin),Karthikeyan Sankaralingam (University of Wisconsin-Madison),Doug Burger (Microsoft Research) (video)

Moguls: a Model to Explore Memory Hierarchy for Throughput Computing
Guangyu Sun (Pennsylvania State University),Christopher J. Hughes,Changkyu Kim (Intel Labs),Jishen Zhao,Cong Xu,Yuan Xie (Pennsylvania State University),Yen-Kuang Chen (Intel Labs) (video)

A Case for Heterogeneous On-Chip Interconnects for CMPs
Asit K. Mishra, N. Vijaykrishnan, Chita R. Das (The Pennsylvania State University) (video)

Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees
Boris Grot,Joel Hestness (The University of Texas at Austin ),Stephen W. Keckler (NVIDIA & The University of Texas at Austin),Onur Mutlu (Carnegie Mellon University)  (video)

DBAR: An Efficient Routing Algorithm to Support Multiple Concurrent Applications in Networks-on-Chip
Sheng Ma (National University of Defense Technology),Natalie Enright Jerger (University of Toronto),Zhiying Wang (National University of Defense Technology) (video)

Session 9A: Photonics (Exhibit Hall 3)
Chair: Engin Ipek, University of Rochester

Combining Memory and a Controller with Photonics through 3D-Stacking to Enable Scalable and Energy-Efficient Systems
Aniruddha N Udipi (University of Utah),Naveen Muralimanohar ( HP),Rajeev Balasubramonian,Al Davis (University of Utah),Norman P Jouppi (HP) (video)

The Role of Optics in Future High Radix Switch Design
Nathan Binkert,Al Davis,Norman P. Jouppi,Moray McLaren,Naveen Muralimanohar,Robert Schreiber (Hewlett-Packard Laboratories),Jung Ho Ahn (Seoul National University) (video)

Session 9B: Power II (J)
Chair: Josep Torrellas, University of Illinois at Urbana-Champaign

Scalable Power Control for Many-Core Architectures Running Multi-threaded Applications
Kai Ma (University of Tennessee and The Ohio State University),Xue Li,Ming Chen (University of Tennessee),Xiaorui Wang (University of Tennessee and The Ohio State University) (video)

Energy-Efficient Cache Design Using Variable-Strength Error-Correcting Codes
Alaa R Alameldeen,Ilya Wagner,Zeshan Chishti,Wei Wu,Chris Wilkerson,Shih-Lien Lu (Intel Corporation)  (video)