Viewing Conference Content

You can view conference presentations and live streams at the ISCA virtual venue (more info on the virtual venue). Note that conference video content is available only to people who register for the conference. Papers are available in the program below.

Welcome Message from the General Co-chairs
José Martínez (Cornell); José Duato (UPV)

Welcome Message from the Program Chair
Lizy K. John (UT Austin)

Welcome Message from the Industry Track Chair
Hsien-Hsin Sean Lee (Facebook)

Day 1: Monday, June 14

10:00 AM – 11:00 AM (EDT/New York): Keynote by Hillery Hunter

7:00 AM (PDT/San Francisco),
16:00 (CEST/Brussels),
22:00 (CST/Beijing)

Hillery Hunter headshot Abstract
Cloud computing today offers a wealth of capacity, elasticity, and computing choice. As architects, we often focus on the speeds and feeds that keep this computing humming along, but in today's climate, security is top of mind. In this talk, we'll explore the journey which has led to at-scale, at-speed confidential computing — capabilities which now enable protection of sensitive data sets, with privacy and authority over computation and data, even when leveraging the advantages of a multi-tenant cloud environment. From custody of digital assets to protection of healthcare records and financial payments, we'll look at how the work of architects is having real-world impact each and every day.


Bio
Hillery Hunter is CTO of IBM Cloud, responsible for technical strategy for IBM's cloud-native and infrastructure offerings. Prior to this role, she served as Director of Accelerated Cognitive Infrastructure in IBM Research, leading a team doing cross-stack (hardware through software) optimization of AI workloads, producing productivity breakthroughs of 40x and greater which were transferred into IBM product offerings. Her technical interests have always been interdisciplinary, spanning from silicon technology through system software, and she has served in technical and leadership roles in memory technology, Systems for AI, and other areas. She is a member of the IBM Academy of Technology and was appointed as an IBM Fellow in 2017. Hillery is a BS, MS, and PhD graduate of the University of Illinois at Urbana–Champaign.

11:00 AM – 12:00 PM (EDT/New York)

8:00 AM (PDT/San Francisco),
17:00 (CEST/Brussels),
23:00 (CST/Beijing)
Session Chair: Hsien-Hsin Sean Lee (Facebook)
11:00 AM – 11:12 AM EDT
Ten Lessons From Three Generations Shaped Google's TPUv4i
Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B. Jablin, George Kurian, James Laudon, Sheng Li, Peter Ma, Xiaoyu Ma, Nishant Patil, Sushma Prasad, Clifford Young, Zongwei Zhou (Google); David Patterson (Google / Berkeley)

11:12 AM – 11:24 AM EDT
Sparsity-Aware and Re-Configurable NPU Architecture for Samsung Flagship Mobile SoC
Jun-Woo Jang, Sehwan Lee, Dongyoung Kim, Hyunsun Park (Samsung Advanced Institute of Technology); Ali Shafiee Ardestani (Samsung Semiconductor); Yeongjae Choi, Channoh Kim, Yoojin Kim, Hyeongseok Yu (Samsung Advanced Institute of Technology); Hamzah Ahmed Ali Abdelaziz (Samsung Semiconductor); Jun-Seok Park, Heonsoo Lee, Dongwoo Lee (Samsung Electronics); Myeong Woo Kim, Hanwoong Jung, Heewoo Nam, Dongguen Lim, Seungwon Lee, Joon Ho Song (Samsung Advanced Institute of Technology); Suknam Kwon (Samsung Electronics); Joseph Hassoun (Samsung Semiconductor); SukHwan Lim (Samsung Electronics); Changkyu Choi (Samsung Advanced Institute of Technology)

11:24 AM – 11:36 AM EDT
Energy Efficiency Boost in the AI-Infused POWER10 Processor
Brian W. Thompto, Dung Q. Nguyen, Jose E. Moreira, Ramon Bertran, Hans Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose (IBM Corp.)

11:36 AM – 11:48 AM EDT
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology
Sukhan Lee, Shin-haeng Kang, Jaehoon Lee, Hyeonsu Kim, Eojin Lee, Seungwoo Seo, Hosang Yoon, Seungwon Lee, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, Seongil O, Anand Iyer, David Wang, Kyomin Sohn, Nam Sung Kim (Samsung Electronics)

11:48 AM – 12:00 PM EDT
Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families
Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, Sean White (AMD)

12:00 PM – 12:45 PM (EDT/New York)

9:00 AM (PDT/San Francisco),
18:00 (CEST/Brussels),
Tue 00:00 (CST/Beijing)
Session Chair: Stijn Eyerman (Intel)
12:00 PM – 12:15 PM EDT
Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-Level Cache Evictions
Mainak Chaudhuri (IIT Kanpur)

12:15 PM – 12:30 PM EDT
Exploiting Page Table Locality for Agile TLB Prefetching
Georgios Vavouliotis (UPC / BSC); Lluc Alvarez (BSC); Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris (NTU Athens); Daniel Jiménez (Texas A&M); Marc Casas (BSC)

12:30 PM – 12:45 PM EDT
A Cost-Effective Entangling Prefetcher for Instructions
Alberto Ros, Alexandra Jimborean (Murcia)
Session Chair: Arkaprava Basu (IISc)
12:00 PM – 12:15 PM EDT
Don't Forget the I/O When Allocating Your LLC
Yifan Yuan (UIUC); Mohammad Alian (Kansas); Yipeng Wang, Ren Wang (Intel Labs); Ilia Kurakin (Intel); Charlie Tai (Intel Labs); Nam Sung Kim (UIUC)

12:15 PM – 12:30 PM EDT
PF-DRAM: A Precharge-Free DRAM Structure
Nezam Rohbani (IPM); Sina Darabi (Sharif); Hamid Sarbazi-Azad (Sharif / IPM)

12:30 PM – 12:45 PM EDT
Efficient Multi-GPU Shared Memory via Automatic Optimization of Fine-Grained Transfers
Harini Muthukrishnan (Michigan); David Nellans, Daniel Lustig (NVIDIA); Jeffrey A. Fessler, Thomas Wenisch (Michigan)

12:45 PM – 1:30 PM (EDT/New York)

9:45 AM (PDT/San Francisco),
18:45 (CEST/Brussels),
Tue 0:45 (CST/Beijing)
Session Chair: Jongse Park (KAIST)
12:45 PM – 1:00 PM EDT
RaPiD: AI Accelerator for Ultra-Low Precision Training and Inference
Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonano, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-hyoun Kim, Siyu Koswatta, Saekyu Lee, Martin Lutz, Silvia Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matt Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan (IBM Corp.)

1:00 PM – 1:15 PM EDT
REDUCT: Keep It Close, Keep It Cool! - Scaling DNN Inference on Multi-Core CPUs with Near-Cache Compute
Anant Nori (Intel Labs); Rahul Bera (ETH Zurich); Shankar Balachandran, Joydeep Rakshit, Om J Omer (Intel Labs); Avishaii Abuhatzera, Belliappa Kuttanna (Intel); Sreenivas Subramoney (Intel Labs)

1:15 PM – 1:30 PM EDT
Communication Algorithm-Architecture Co-Design for Distributed Deep Learning
Jiayi Huang (UCSB); Pritam Majumder, Sungkeun Kim, Abdullah Muzahid, Ki Hwan Yum, Eun Jung Kim (Texas A&M)
Session Chair: Dam Sunwoo (Arm)
12:45 PM – 1:00 PM EDT
Vector Runahead
Ajeya Naithani (UGhent); Sam Ainsworth (Edinburgh); Timothy Jones (Cambridge); Lieven Eeckhout (UGhent)

1:00 PM – 1:15 PM EDT
Unlimited Vector Extension with Data Streaming Support
João Domingos (INESC-ID / Instituto Superior Técnico, Universidade de Lisboa); Nuno Neves (INESC-ID / Instituto de Telecomunicações); Nuno Roma and Pedro Tomás (INESC-ID / Instituto Superior Técnico, Universidade de Lisboa)

1:15 PM – 1:30 PM EDT
Speculative Vectorisation with Selective Replay
Peng Sun (Cambridge); Giacomo Gabrielli (Arm); Timothy Jones (Cambridge)

1:30 PM – 3:00 PM (EDT/New York)

10:30 AM (PDT/San Francisco),
19:30 (CEST/Brussels),
Tue 01:30 (CST/Beijing)

This year marks the 50th anniversary of the Intel 4004, the world's first microprocessor and an engineering achievement that continues to evolve at a blistering pace. This technical and visionary panel offers the rare opportunity to bring together microprocessor experts who have been part of this evolution and watch them look back at 5 decades of achievement. We expect a lively discussion as the panel exchanges ideas about what the microprocessor might be in another 25 years (assuming it still exists in a recognizable form). The panelists collectively span most major microprocessor architectures and spent their careers at companies such as Acorn/Arm, Tensilica, Centaur, IBM, and Intel:

  • Federico Faggin: designer of the first commercial microprocessor (Intel 4004), awarded National Medal of Technology and Innovation
  • John Hennessy: co-founder of MIPS Technologies, pioneer of RISC (shared Turing award), Chairman of Alphabet, 10th President of Stanford, author of popular architecture book
  • David Patterson: led Berkeley RISC project (which became the basis for Sun SPARC), pioneer of RISC (shared Turing award), currently at Google, author of popular architecture book
  • Glenn Henry: designed computers spanning from IBM mainframes to personal computers and custom x86 CPUs, IBM Fellow, Sr. VP Dell, Pres. Centaur Technology
  • Kathy Papermaster: 26 years of experience at IBM, led multiple IBM projects, including the Cell Broadband Engine microprocessor
  • Lee Smith: co-founded Arm, led development of software tools at Acorn and Arm, Arm Fellow
  • Shekhar Borkar: directed Intel microprocessor research for 34 years, former Intel Fellow, currently at Qualcomm
  • Chris Rowen: co-founder of MIPS Technologies, Tensilica, Babblelabs, pioneer of microprocessor hardware/software co-design

The panel will be moderated by J. Scott Gardner, an independent microprocessor-technology analyst. Panel Chair: Lizy K. John.

8:00 PM – 9:00 PM (EDT/New York)

5:00 PM (PDT/San Francisco),
Tue 02:00 (CEST/Brussels),
Tue 08:00 (CST/Beijing)
Session Chair: Nathan Beckmann (CMU)
8:00 PM – 8:15 PM EDT
ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-Based Near-Memory Processing with Inter-DIMM Broadcast
Weiyi Sun, Zhaoshi Li, Shouyi Yin, Shaojun Wei, Leibo Liu (Tsinghua)

8:15 PM – 8:30 PM EDT
Sieve: Scalable In-Situ DRAM-Based Accelerator Designs for Massively Parallel k-mer Matching
Lingxi Wu, Rasool Sharifi, Marzieh Lenjani, Kevin Skadron, Ashish Venkat (Virginia)

8:30 PM – 8:45 PM EDT
FORMS: Fine-Grained Polarized ReRAM-Based In-Situ Computation for Mixed-Signal DNN Accelerator
Geng Yuan (Northeastern); Payman Behnam (Georgia Tech); Zhengang Li (Northeastern); Ali Shafiee (Samsung); Sheng Lin, Xiaolong Ma (Northeastern); Hang Liu (Stevens); Xuehai Qian (USC); Mahdi Nazm Bojnordi (Utah); Yanzhi Wang (Northeastern); Caiwen Ding (UConn)

8:45 PM – 9:00 PM EDT
BOSS: Bandwidth-Optimized Search Accelerator for Storage-Class Memory
Jun Heo, Seungyul Lee, Sunhong Min, Yeonhong Park, Sung Jun Jung, Tae Jun Ham, Jae W. Lee (SNU)
Session Chair: Jian Chen (Alibaba)
8:00 PM – 8:15 PM EDT
SATORI: Efficient and Fair Resource Partitioning by Sacrificing Short-Term Benefits for Long-Term Gains
Rohan Basu Roy, Tirthak Patel, Devesh Tiwari (Northeastern)

8:15 PM – 8:30 PM EDT
Confidential Serverless Made Efficient with Plug-In Enclaves
Mingyu Li, Yubin Xia, Haibo Chen (Shanghai Jiao Tong)

8:30 PM – 8:45 PM EDT
Flex: High-Availability Datacenters with Zero Reserved Power
Chaojie Zhang (Chicago); Alok Gautam Kumbhare (Microsoft Research); Ioannis Manousakis (Microsoft); Deli Zhang, Pulkit Misra (Microsoft Research); Rod Assis, Kyle Woolcock, Nithish Mahalingam, Brijesh Warrier, David Gauthier, Lalu Kunnath, Steve Solomon, Osvaldo Morales, Marcus Fontoura (Microsoft); Ricardo Bianchini (Microsoft Research)

8:45 PM – 9:00 PM EDT
BlockMaestro: Enabling Programmer-Transparent Task-Based Execution in GPU Systems
Amirali Abdolrashidi, Hodjat Asghari Esfeden, Ali Jahanshahi, Kaustubh Singh, Nael Abu-Ghazaleh, Daniel Wong (UC Riverside)

9:00 PM – 9:45 PM (EDT/New York)

6:00 PM (PDT/San Francisco),
Tue 03:00 (CEST/Brussels),
Tue 09:00 (CST/Beijing)
Session Chair: Alaa Alameldeen (Simon Fraser)
9:00 PM – 9:15 PM EDT
Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data
Jose Rodrigo Sanchez Vicarte, Pradyumna Shome, Nandeeka Nayak (UIUC); Caroline Trippel (Stanford); Adam Morrison (Tel Aviv University); David Kohlbrenner (Washington); Christopher Fletcher (UIUC)

9:15 PM – 9:30 PM EDT
I See Dead μops: Leaking Secrets via Intel/AMD Micro-Op Caches
Xida Ren, Logan G. Moody (Virginia); Mohammadkazem Taram (UCSD); Matthew Jordan (Virginia); Dean M. Tullsen (UCSD); Ashish Venkat (Virginia)

9:30 PM – 9:45 PM EDT
TimeCache: Using Time to Eliminate Cache Side Channels when Sharing Software
Divya Ojha, Sandhya Dwarkadas (Rochester)
Session Chair: Saugata Ghose (UIUC)
9:00 PM – 9:15 PM EDT
Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees
Arun Subramaniyan, Jack Wadden, Kush Goliya, Nathan Ozog, Xiao Wu, Satish Narayanasamy, David Blaauw, Reetuparna Das (Michigan)

9:15 PM – 9:30 PM EDT
Aurochs: An Architecture for Dataflow Threads
Matt Vilim, Alexander Rucker, Kunle Olukotun (Stanford)

9:30 PM – 9:45 PM EDT
PipeZK: Accelerating Zero-Knowledge Proof with a Pipelined Architecture
Ye Zhang (Peking / Shanghai Tree-Graph Blockchain Research Institute); Shuo Wang (Peking); Xian Zhang (Microsoft Research); Jiangbin Dong (Xi'an Jiaotong University); Xingzhong Mao (Institute for Interdisciplinary Information Core Technology); Fan Long (Toronto); Cong Wang (Imo.vc); Dong Zhou, Mingyu Gao (Tsinghua); Guangyu Sun (Peking)

9:45 PM – 10:30 PM (EDT/New York)

6:45 PM (PDT/San Francisco),
Tue 03:45 (CEST/Brussels),
Tue 09:45 (CST/Beijing)

The biological and life sciences present a wealth of sophisticated and efficient computing substrates and, as a consequence, have been the source of inspiration for next-generation computing. This panel will cover emerging opportunities for research cross-pollination between the life sciences and computing technologies. Discussions will focus on topics ranging from machine learning and neural networks, brain computer interfaces, molecular & DNA computing, to the opportunities that they present for classical computing and acceleration, as well as emerging neuromorphic and quantum computing technologies



Day 2: Tuesday, June 15

10:00 AM – 11:00 AM (EDT/New York): SIGARCH/TCCA Business Meeting

7:00 AM (PDT/San Francisco),
16:00 (CEST/Brussels),
22:00 (CST/Beijing)
Location: Lonja Room (What Is Lonja?)

11:00 AM – 12:00 PM (EDT/New York): Keynote by Monica Lam

8:00 AM (PDT/San Francisco),
17:00 (CEST/Brussels),
23:00 (CST/Beijing)

Monica Lam headshot Abstract
Virtual assistants today provide a proprietary voice interface for over 100,000 skills and are built with a 100,000-strong workforce. This talk presents the Stanford open virtual assistant initiative that uses deep learning to lower the development cost, improve the scalability and robustness, and to add dialogue capabilities to enhance the user experience. The research results are encapsulated in the Genie toolset to make voice interfaces as easy to build as web interfaces, and can thus accelerate the growth of an open worldwide voice web. In addition, the open-source assistant is federated to protect user privacy; it is distributed with Home Assistant, an open-source local gateway for home IoTs with over 100,000 users.


Bio
Dr. Monica Lam has been a Professor of Computer Science at Stanford University since 1988, and is the Faculty Director of the Stanford Open Virtual Assistant Laboratory. She leads the Genie open virtual assistant project, which aims to advance and democratize voice assistant technology, keep the voice web open, and protect the privacy of consumers.

Prof. Lam is a member of the National Academy of Engineering and an ACM Fellow. She has won numerous best paper awards, and has published over 150 papers on many topics: natural language processing, machine learning, HCI, compilers, computer architecture, operating systems, and high-performance computing. She is a co-author of the "Dragon Book", the definitive text on compiler technology. She received a B.Sc. from University of British Columbia (1980) and a Ph.D. from Carnegie Mellon University (1987).

12:00 PM – 1:00 PM (EDT/New York)

9:00 AM (PDT/San Francisco),
18:00 (CEST/Brussels),
Wed 00:00 (CST/Beijing)
Session Chair: Timothy Jones (Cambridge)
12:00 PM – 12:15 PM EDT
Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures
Ajay Brahmakshatriya (MIT); Emily Furst (Washington); Victor A. Ying, Claire Hsu, Changwan Hong (MIT); Max Ruttenberg (Washington); Yunming Zhang (MIT); Dai Cheol Jung, Dustin Richmod, Michael Taylor (Washington); Julian Shun (MIT); Mark Oskin (Washington); Daniel Sanchez, Saman Amarasinghe (MIT)

12:15 PM – 12:30 PM EDT
Supporting Legacy Libraries on Non-Volatile Memory: A User-Transparent Approach
Chencheng Ye (HUST); Yuanchao Xu, Xipeng Shen (NCSU); Xiaofei Liao, Hai Jin (HUST); Yan Solihin (UCF)

12:30 PM – 12:45 PM EDT
Execution Dependence Extension (EDE): ISA Support for Eliminating Fences
Thomas Shull (Oracle Labs); Ilias Vougioukas, Nikos Nikoleris, Wendy Elsasser (Arm Research); Josep Torrellas (UIUC)

12:45 PM – 1:00 PM EDT
Hetero-ViTAL: A Virtualization Stack for Heterogeneous FPGA Clusters
Yue Zha, Jing Li (UPenn)
Session Chair: Jayneel Gandhi (VMware)
12:00 PM – 12:15 PM EDT
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
Lois Orosa (ETH Zurich); Yaohua Wang (NUDT); Mohammad Sadrosadati (IPM); Jeremie Kim, Haocong Luo, Kaveh Razavi, Juan Gómez Luna, Ivan Puddu, Hasan Hassan, Minesh Patel, Nika Mansouri Ghiasi (ETH Zurich); Saugata Ghose (UIUC); Onur Mutlu (ETH Zurich)

12:15 PM – 12:30 PM EDT
NVOverlay: Enabling Efficient and Scalable High-Frequency Snapshotting to NVM
Ziqi Wang (CMU); Chul-Hwan Choo (Samsung); Michael A. Kozuch (Intel Labs / CMU); Todd C. Mowry (CMU); Gennady Pekhimenko (Toronto); Vivek Seshadri (Microsoft Research India); Dimitrios Skarlatos (CMU)

12:30 PM – 12:45 PM EDT
Rebooting Virtual Memory with Midgard
Siddharth Gupta, Atri Bhattacharyya, Yunho Oh (EPFL); Abhishek Bhattacharjee (Yale); Babak Falsafi, Mathias Payer (EPFL)

12:45 PM – 1:00 PM EDT
Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication
Adarsh Patil, Vijay Nagarajan (Edinburgh); Rajeev Balasubramonian (Utah); Nicolai Oswald (Edinburgh)

1:00 PM – 1:45 PM (EDT/New York)

10:00 AM (PDT/San Francisco),
19:00 (CEST/Brussels),
Wed 1:00 (CST/Beijing)
Session Chair: Lisa Wu Wills (Duke)
1:00 PM – 1:15 PM EDT
Enabling Compute-Communication Overlap in Distributed Deep Learning Training Platforms
Saeed Rashidi, Matthew Denton (Georgia Tech); Srinivas Sridharan (Facebook); Sudarshan Srinivasan (Intel); Amoghavarsha Suresh (Stony Brook); Jade Nie (Facebook); Tushar Krishna (Georgia Tech)

1:15 PM – 1:30 PM EDT
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators
Qijing Huang, Minwoo Kang, Grace Dinh, Thomas Norell (Berkeley); Aravind Kalaiah (Facebook); James Demmel, John Wawrzynek, Yakun Sophia Shao (Berkeley)

1:30 PM – 1:45 PM EDT
η-LSTM: Co-Designing Highly-Efficient Large LSTM Training via Exploiting Memory-Saving and Architectural Design Opportunities
Xingyao Zhang (Washington / Houston); Haojun Xia, Donglin Zhuang, Hao Sun (Sydney); Xin Fu (Houston); Michael Taylor (Washington); Shuaiwen Leon Song (Sydney)
Session Chair: Scott Beamer (UCSC)
1:00 PM – 1:15 PM EDT
FlexMiner: A Pattern-Aware Accelerator for Graph Pattern Mining
Xuhao Chen, Tianhao Huang, Shuotao Xu, Thomas Bourgeat, Chanwoo Chung, Arvind (MIT)

1:15 PM – 1:30 PM EDT
PolyGraph: Exposing the Value of Flexibility for Graph Processing Accelerators
Vidushi Dadu, Sihao Liu, Tony Nowatzki (UCLA)

1:30 PM – 1:45 PM EDT
Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses
Mikhail Asiatici, Paolo Ienne (EPFL)

1:45 PM – 2:30 PM (EDT/New York)

10:45 AM (PDT/San Francisco),
19:45 (CEST/Brussels),
Wed 01:45 (CST/Beijing)

Quantum computers promise to solve a class of commercial and scientifically important problems that are beyond the abilities of classical computers. Computing, whether it is conventional or quantum, is ultimately a series of transformations, ranging from algorithms at the top, to devices at the bottom. Over the past three decades, there has been significant progress in the field of quantum algorithms (which relies on mathematical properties of quantum states) and quantum devices (which relies on physical properties of materials), however, the role of computer systems (which transforms mathematics into physics) has only recently started to gain prominence.

This panel will discuss the role and the challenges for the architecture and compiler community in making quantum computing practical.

Panelist bios:

  • Ali Javadi-Abhari is a Principal Research Staff Member at IBM. His research interests are in compiler and architecture issues in near-term quantum computing. He was the main architect of the Scaffold quantum programming language and the Qiskit quantum information science package. He leads the compilation sub-thrust of the Co-design Center for Quantum Advantage, as part of the National Quantum Initiative. He received his PhD in computer science from Princeton in 2017.
  • Caroline Collange is a research scientist at Inria Rennes in France since 2012. Her research interests include compiler optimization and microarchitecture for quantum computers and GPUs. She was previously a post-doc researcher at UFMG, Brazil and an assistant professor at ENS Lyon, France.
  • Kenneth Brown is a Professor of Electrical and Computer Engineering and Physics at Duke University. He is the Director of the National Science Foundation Software-Tailored Architectures for Quantum co-design (STAQ) project.
  • Devesh Tiwari directs the Goodwill Computing Lab at Northeastern University (Boston campus). Before joining Northeastern, Devesh was a staff scientist at the United States Department of Energy Oak Ridge National Laboratory. His research interests are around HPC and data center systems, and quantum computing. He is an Associate Editor for Transactions on Parallel and Distributed Systems (TPDS), Transactions on Storage (ToS) and Journal of Parallel & Distributed Computing (JPDC).
  • The panel will be moderated by Moinuddin Qureshi, Professor of Computer Science at Georgia Tech.

8:00 PM – 9:00 PM (EDT/New York)

5:00 PM (PDT/San Francisco),
Wed 02:00 (CEST/Brussels),
Wed 08:00 (CST/Beijing)
Session Chair: Josep Torrellas (UIUC)
8:00 PM – 8:15 PM EDT
Cost-Efficient Overclocking in Immersion-Cooled Datacenters
Majid Jalili (UT Austin); Ioannis Manousakis, Íñigo Goiri, Pulkit Misra, Ashish Raniwala, Husam Alissa, Bharath Ramakrishnan (Microsoft); Phillip Tuma (3M); Christian Belady, Marcus Fontoura, Ricardo Bianchini (Microsoft)

8:15 PM – 8:30 PM EDT
CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing
Gyu-Hyeon Lee, Seongmin Na, Il-Kwon Byun, Dongmoon Min, Jangwoo Kim (SNU)

8:30 PM – 8:45 PM EDT
Superconducting Computing with Alternating Logic Elements
Georgios Tzimpragos (UCSB); Jennifer Volk (UCSB); Alexander Wynn (MIT Lincoln Lab); James Smith; Tim Sherwood (UCSB)

8:45 PM – 9:00 PM EDT
Failure Sentinels: Ubiquitous Just-in-Time Intermittent Computation via Low-Cost Hardware Support for Voltage Monitoring
Harrison Williams, Michael Moukarzel, Matthew Hicks (Virginia Tech)
Session Chair: Divya Majahan (Microsoft)
8:00 PM – 8:15 PM EDT
SPACE: Locality-Aware Processing in Heterogeneous Memory for Personalized Recommendations
Hongju Kal, Seokmin Lee, Gun Ko, Won Woo Ro (Yonsei)

8:15 PM – 8:30 PM EDT
ELSA: Hardware-Software Co-Design for Efficient, Lightweight Self-Attention Mechanism in Neural Networks
Tae Jun Ham, Yejin Lee, Seong Hoon Seo, Soosung Kim, Hyunji Choi, Sung Jun Jung, Jae W. Lee (SNU)

8:30 PM – 8:45 PM EDT
Cambricon-Q: A Hybrid Architecture for Efficient Training
Yongwei Zhao, Chang Liu, Zidong Du, Qi Guo, Xing Hu, Yimin Zhuang, Zhenxing Zhang, Xinkai Song, Wei Li, Xishan Zhang (ICT, CAS); Ling Li (Institute of Software, CAS); Zhiwei Xu (ICT, CAS), Tianshi Chen (Cambricon)

8:45 PM – 9:00 PM EDT
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-Centric Notation
Liqiang Lu (Peking); Naiqing Guan (Toronto); Yuyue Wang, Liancheng Jia, Zizhang Luo (Peking); Jieming Yin (Lehigh); Jason Cong (UCLA); Yun Liang (Peking)

9:00 PM – 9:45 PM (EDT/New York)

6:00 PM (PDT/San Francisco),
Wed 03:00 (CEST/Brussels),
Wed 09:00 (CST/Beijing)
Session Chair: Esha Choukse (Microsoft)
9:00 PM – 9:15 PM EDT
Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications
Tanvir Ahmed Khan (Michigan); Dexin Zhang (USTC); Akshitha Sriraman (Michigan); Joseph Devietti (UPenn); Gilles A. Pokam (Intel); Heiner Litz (UCSC); Baris Kasikci (Michigan)

9:15 PM – 9:30 PM EDT
Quantifying Server Memory Frequency Margin and Using It to Improve Performance in HPC Systems
Da Zhang, Gagandeep Panwar (Virginia Tech); Jagadish Kotra (AMD Research); Nathan DeBardeleben, Sean Blanchard (Los Alamos); Xun Jian (Virginia Tech)

9:30 PM – 9:45 PM EDT
Revamping Storage Class Memory With Hardware Automated Memory-Over-Storage Solution
Jie Zhang, Miryeong Kwon, Donghyun Gouk, Sungjoon Koh (KAIST); Nam Sung Kim (UIUC); Mahmut Taylan Kandemir (Penn State); Myoungsoo Jung (KAIST)
Session Chair: EJ Kim (TAMU)
9:00 PM – 9:15 PM EDT
NASGuard: A Novel Accelerator Architecture for Robust Neural Architecture Search (NAS) Networks
Xingbin Wang (State Key Laboratory of Information Security, Institute of Information Engineering, CAS); Boyan Zhao and Rui Hou (Institute of Information Engineering, CAS); Amro Awad (NCSU / UCF); Zhihong Tian (Guangzhou); Dan Meng (Institute of Information Engineering, CAS)

9:15 PM – 9:30 PM EDT
NASA: Accelerating Neural Network Design with a NAS Processor
Xiaohan Ma, Chang Si, Ying Wang (ICT, CAS); Cheng Liu (State Key Laboratory of Computer Architecture, ICT, CAS); Lei Zhang (ICT, CAS)

9:30 PM – 9:45 PM EDT
PMNet: In-Network Data Persistence
Korakit Seemakhupt, Sihang Liu, Yasas Senevirathne (Virginia); Muhammad Shahbaz (Stanford); Samira Khan (Virginia)

9:45 PM – 10:30 PM (EDT/New York)

6:45 PM (PDT/San Francisco),
Wed 03:45 (CEST/Brussels),
Wed 09:45 (CST/Beijing)

The new era of computer architecture heavily focuses on cross-stack system design with heterogeneous accelerators and new memory and storage systems. This change brings the opportunity and excitement of innovating new systems, but also introduces the challenge of building tools and system components necessary to evaluate radically new designs. The question we will discuss on this panel is the following: how should the architecture community propose, validate, and prototype ideas in this new era of computer architecture to maximize the impact?



Day 3: Wednesday, June 16

10:00 AM – 11:00 AM (EDT/New York): Keynote by Pradeep Dubey

7:00 AM (PDT/San Francisco),
16:00 (CEST/Brussels),
22:00 (CST/Beijing)

Pradeep Dubey headshot Abstract
Artificial intelligence (AI) is touching, if not transforming, every aspect of our lives. Fast-evolving AI algorithms are driving demand for general-purpose computing that cannot be met by "business as usual" engineering. At the same time, programmers are often data scientists, not computer scientists; expecting programmers to figure out increasingly complex hardware on their own just doesn't work. Architects are therefore needed more than ever – chip architects to create new processors, systems architects to design new data centers, software architects to design new frameworks, and AI architects to churn out new models and new algorithms. Are we up to the task? Or do we need to augment human architects with AI to meet the challenge?


Bio
Pradeep K. Dubey is an Intel Senior Fellow and director of the Parallel Computing Lab, a part of the Intel Labs organization at Intel Corporation. He leads a team of top researchers focused on state-of-the-art research in parallel computing. Dubey and his team are responsible for defining computer architectures that can efficiently handle emerging machine learning/artificial intelligence, traditional HPC applications for data-centric computing environments, and deriving product differentiation opportunities for Intel's CPU and GPU processing platforms. Dubey previously worked at IBM's T.J. Watson Research Center. Dubey has made significant contributions to the design, architecture and application performance of various microprocessors, including the IBM Power PC, the Intel386™, Intel486™, Intel® Pentium®, and Intel Xeon® processors. He holds 36 patents and has published more than 100 peer-reviewed technical papers. In 2012, Dubey was honored with an Intel Achievement Award for breakthroughs in parallel computing research, and was honored with the Outstanding Electrical and Computer Engineer Award from Purdue University in 2014. Dubey holds a Ph.D. in electrical engineering from Purdue University. He is also a Fellow of IEEE

11:00 AM – 12:00 PM (EDT/New York): Awards Ceremony

8:00 AM (PDT/San Francisco),
17:00 (CEST/Brussels),
23:00 (CST/Beijing)
Location: Lonja Room (What Is Lonja?)

12:00 PM – 1:00 PM (EDT/New York)

9:00 AM (PDT/San Francisco),
18:00 (CEST/Brussels),
Thu 00:00 (CST/Beijing)
Session Chair: Swamit Tannu (Wisconsin)
12:00 PM – 12:15 PM EDT
Exploiting Long Distance Interactions and Tolerating Atom Loss in Neutral Atom Quantum Architectures
Jonathan M. Baker, Andrew Litteken, Casey Duckering, Henry Hoffmann, Hannes Bernien, Fred Chong (Chicago)

12:15 PM – 12:30 PM EDT
Software-Hardware Co-Optimization for Computational Chemistry on Superconducting Quantum Processors
Gushu Li (UCSB); Yunong Shi (Chicago); Ali Javadi-Abhari (IBM)

12:30 PM – 12:45 PM EDT
Designing Calibration and Expressivity-Efficient Instruction Sets for Quantum Computing
Lingling Lao (University College London); Prakash Murali, Margaret R. Martonosi (Princeton); Dan Browne (University College London)

12:45 PM – 1:00 PM EDT
Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics
Kyle Shiflett, Avinash Karanth (Ohio University); Razvan Bunescu (UNC Charlotte); Ahmed Louri (GWU)
Session Chair: Reetuparna Das (Michigan)
12:00 PM – 12:15 PM EDT
IntroSpectre: A Pre-Silicon Framework for Discovery and Analysis of Transient Execution Vulnerabilities
Moein Ghaniyoun, Kristin Barber, Yinqian Zhang, Radu Teodorescu (Ohio State)

12:15 PM – 12:30 PM EDT
Maya: Using Formal Control to Obfuscate Power Side Channels
Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Alex Schwing, Josep Torrellas (UIUC)

12:30 PM – 12:45 PM EDT
Demystifying the System Vulnerability Stack: Transient Fault Effects Across the Layers
George Papadimitriou, Dimitris Gizopoulos (University of Athens)

12:45 PM – 1:00 PM EDT
No-FAT: Architectural Support for Low Overhead Memory Safety Checks
Mohamed Tarek Ibn Ziad, Miguel Arroyo, Evgeny Manzhosov, Ryan Piersma (Columbia); Simha Sethumadhavan (Columbia / Chip Scan)

1:00 PM – 1:45 PM (EDT/New York)

10:00 AM (PDT/San Francisco),
19:00 (CEST/Brussels),
Thu 1:00 (CST/Beijing)
Session Chair: Martin Maas (Google)
1:00 PM – 1:15 PM EDT
Ghost Routing to Enable Oblivious Computation on Memory-Centric Networks
Yeonju Ro, Seongwook Jin, Jaehyuk Huh, John Kim (KAIST)

1:15 PM – 1:30 PM EDT
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
Ataberk Olgun (TOBB); Abdullah Giray Yaglikci, Minesh Patel, Jeremie Kim (ETH Zurich); Fatma Nisa Bostanci (TOBB); Haocong Luo (ETH Zurich); Nandita Vijaykumar (Toronto); Oguz Ergin (TOBB); Onur Mutlu (ETH Zurich)

1:30 PM – 1:45 PM EDT
A RISC-V In-Network Accelerator for Flexible High-Performance Low-Power Packet Processing
Salvatore Di Girolamo, Andreas Kurth, Alexandru Calotoiu, Thomas Benz, Timo Schneider (ETH Zurich); Jakub Beránek (Technical University of Ostrava); Luca Benini, Torsten Hoefler (ETH Zurich)
Session Chair: Radu Teodorescu (Ohio State)
1:00 PM – 1:15 PM EDT
Leaky Buddies: Cross-Component Covert Channels on Integrated CPU-GPU Systems
Sankha Baran Dutta (UC Riverside); Hoda Naghibijouybari (Binghamton); Nael Abu-Ghazaleh (UC Riverside); Andres Marquez, Kevin Barker (Pacific Northwest National Lab)

1:15 PM – 1:30 PM EDT
IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors
Jawad Haj-Yahya, Jeremie Kim, Ivan Puddu, Abdullah Giray Yaglikci, Mohammed Alser, Lois Orosa, Juan Gómez Luna, Onur Mutlu (ETH Zurich)

1:30 PM – 1:45 PM EDT
ZeRØ: Zero-Overhead Resilient Operation Under Pointer Integrity Attacks
Mohamed Tarek Ibn Ziad, Miguel Arroyo, Evgeny Manzhosov (Columbia); Simha Sethumadhavan (Columbia / Chip Scan)

1:45 PM – 2:30 PM (EDT/New York)

10:45 AM (PDT/San Francisco),
19:45 (CEST/Brussels),
Thu 01:45 (CST/Beijing)

The 50 years of microprocessor technologies have tremendously advanced all aspects of our lives. This panel provides us the space to examine the powerful technologies we are developing, responsibilities and societal impacts we must keep in mind when developing the technologies. This panel will discuss the societal challenges brought by digital technologies — the ever-increasing carbon emissions from computing, bias and fairness issues facing AI technologies, and the disparate social justice. What underinvested research directions should the community focus on in order to build environmentally-sustainable, socially-responsible technologies for the next decades to come?

Panelist bios:

  • Srilatha (Bobbie) Manne has worked in the computer industry for over two decades in both industrial research labs and product teams at Compaq, Intel, AMD and Cavium. She is currently a Principal Hardware Engineer in the Azure Hardware Systems and Infrastructure group at Microsoft. Her work has focused on power and performance analysis from processor microarchitecture to data centers. Srilatha has continued to publish while in industry, and has more than 29 patents granted. She was also the recipient of the 2014 ISCA Influential Paper Award for her work on power reduction in processor design. Srilatha has been active in the academic community through service on program committees, serving as General Chair for ISCA 2019, and giving a keynote address at MICRO 2020. Her latest passion is collaborating with an interdisciplinary group of engineers and technical experts to develop a more sustainable computational ecosystem from client devices to data centers.
  • Partha Ranganathan is currently a VP, technical Fellow at Google where he is the area technical lead for hardware and datacenters, designing systems at scale. Prior to this, he was a HP Fellow and Chief Technologist at Hewlett Packard Labs where he led their research on systems and data centers. Partha has worked on several interdisciplinary systems projects with broad impact on both academia and industry, including widely-used innovations in energy-aware user interfaces, heterogeneous multi-cores, power-efficient and sustainable servers, domain-specific accelerators, and disaggregated and data-centric data centers. He has published extensively (including being the co-author on the popular "Datacenter as a Computer" textbook), is a co-inventor on more than 100 patents, and has been recognized with numerous awards. He has been named a top-15 enterprise technology rock star by Business Insider, one of the top 35 young innovators in the world by MIT Tech Review, and is a recipient of the ACM SIGARCH Maurice Wilkes award, Rice University's Outstanding Young Engineering Alumni award, and the IIT Madras distinguished alumni award. He is also a Fellow of the IEEE and ACM, and is currently on the board of directors for OpenCompute.
  • Shane Greenstein is the Martin Marshall Professor of Business Administration and co-chair of the HBS Digital Initiative. He teaches in the Technology, Operations and Management Unit. Encompassing a wide array of questions about computing, communication, and Internet markets, Professor Greenstein's research extends from economic measurement and analysis to broader issues. His most recent book, How the Internet Became Commercial (2015, Princeton University Press), won the 2016 Schumpeter Prize for best book. He also publishes commentary on his blog, Digitopoly, and many media outlets cover his work. Professor Greenstein previously taught at the Kellogg School of Management, Northwestern University, and at the University of Illinois Urbana–Champaign. He received his PhD from Stanford University, and his BA from University of California at Berkeley, both in economics. He continues to receive a daily education in life from his wife and children.
  • Carole-Jean Wu is currently a Technical Lead at Facebook AI Research. Her research lies in the domain of computer architecture. Her work has included designing energy- and memory-efficient systems, building and optimizing systems for machine learning execution at-scale. She is passionate about tackling system challenges to enable efficient, responsible AI execution. Carole-Jean chairs the MLPerf Recommendation Benchmark Advisory Board, co-chaired MLPerf Inference, and serves on the MLCommons Board as a director. Carole-Jean is a tenured Associate Professor at ASU (on leave). She received her M.A. and Ph.D. from Princeton and B.Sc. from Cornell. She is the recipient of the NSF CAREER Award, Distinction of Honorable Mention of the CRA Anita Borg Early Career Award, the IEEE Young Engineer of the Year Award, the Science Foundation Arizona Bisgrove Early Career Scholarship, and the Intel PhD Fellowship, among a number of IEEE Micro Top Picks, IEEE Best Paper awards.
  • Sarah Bird leads the responsible and ethical development of the Azure AI Cognitive Services at Microsoft. As an expert in responsible AI implementation, she contributes to the development and adoption of responsible AI principles, best practices, and technologies company-wide. Sarah led the product development of responsible AI tools including Fairlearn, SmartNoise and InterpretML. She is an active member of the Microsoft AETHER committee and contributed to the creation of the Microsoft Responsible AI Standard. Sarah was one of the founding researchers in the Microsoft FATE research group. She has a Ph.D. in Computer Science from UC Berkeley advised by Dave Patterson, Krste Asanovic, and Burton Smith.

8:00 PM – 9:00 PM (EDT/New York)

5:00 PM (PDT/San Francisco),
Thu 02:00 (CEST/Brussels),
Thu 08:00 (CST/Beijing)
Session Chair: Tushar Krishna (Georgia Tech)
8:00 PM – 8:15 PM EDT
NN-Baton: DNN Workload Orchestration and Chiplet Granularity Exploration for Multichip Accelerators
Zhanhong Tan, Hongyu Cai (Tsinghua); Runpei Dong (Xi’an Jiaotong University); Kaisheng Ma (Tsinghua)

8:15 PM – 8:30 PM EDT
SNAFU: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture
Graham Gobieski, Oguz Atli, Ken Mai, Brandon Lucia, Nathan Beckmann (CMU)

8:30 PM – 8:45 PM EDT
SARA: Scaling a Reconfigurable Dataflow Accelerator
Yaqi Zhang, Nathan Zhang, Tian Zhao, Matt Vilim, Muhammad Shahbaz, Kunle Olukotun (Stanford)

8:45 PM – 9:00 PM EDT
HASCO: Towards Agile HArdware and Software CO-design for Tensor Computation
Qingcheng Xiao, Size Zheng, Bingzhe Wu (Center for Energy-Efficient Computing and Applications, Peking); Pengcheng Xu (Peking); Xuehai Qian (USC); Yun Liang (Center for Energy-Efficient Computing and Applications, Peking )
Session Chair: Shuaiwen Song (Sydney)
8:00 PM – 8:15 PM EDT
SpZip: Architectural Support for Effective Data Compression In Irregular Applications
Yifan Yang (MIT); Joel Emer (MIT / NVIDIA); Daniel Sanchez (MIT)

8:15 PM – 8:30 PM EDT
Dual-Side Sparse Tensor Core
Yang Wang (UESTC / Microsoft Research); Chen Zhang (Microsoft Research); Zhiqiang Xie (ShanghaiTech University); Cong Guo (Shanghai Jiao Tong); Yunxin Liu (Microsoft Research); Jingwen Leng (Shanghai Jiao Tong)

8:30 PM – 8:45 PM EDT
RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging
Chao-Tsung Huang (National Tsing Hua University)

8:45 PM – 9:00 PM EDT
GoSPA: An Energy-Efficient High-Performance Globally Optimized SParse Convolutional Neural Network Accelerator
Chunhua Deng, Yang Sui, Siyu Liao (Rutgers); Xuehai Qian (USC); Bo Yuan (Rutgers)

9:00 PM – 10:30 PM (EDT/New York)

6:00 PM (PDT/San Francisco),
Thu 03:00 (CEST/Brussels),
Thu 09:00 (CST/Beijing)

In the last decade, the computer architecture research community has grown dramatically. There are now many young faculty and graduate students in many academic institutions. With the seismic changes taking place in our technical field, we have an opportunity to use these creative minds to crack some of the many computer systems architecture challenges. To do so, researchers need to be aware of the opportunities available to them. This panel will include leaders from industry and funding agencies who will help the audience reflect on the existing funding and research opportunities, priorities and future trends.